RTL Design
Register Transfer Level Design: is an abstract methodology of defining your system or design using Hardware Description Languages (HDL), primarily Verilog and System Verilog.
Overview:
1. RTL Introduction
Verilog:
2. Verilog Introduction
3. Datatypes and operators
4. Properties
5. case statement
6. always block
7. guidelines for synthesizable designs
8. sequential designs
9. Functions and Tasks
In this post I will explain the basics on RTL Designing, and then lets dive deep into Verilog and System Verilog HDLs.
Remember: There is no digital system in this world, you cannot design using RTL.
Overview:
1. RTL Introduction
Verilog:
2. Verilog Introduction
3. Datatypes and operators
4. Properties
5. case statement
6. always block
7. guidelines for synthesizable designs
8. sequential designs
9. Functions and Tasks
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