About Me

Hello, I am Ankit Berde, and currently working in SoCtronics Technologies Pvt Ltd, Hyderabad as Logic Design Engineer. Following is my background information:

Education qualification:
Bachelor of Engineering in Electronics and Tele-communication from Mumbai University [July 2012 - July 2016].

Career:
Engineer at SoCtronics Technologies Pvt Ltd, Hyderabad [January 2018 - Present]
During my work, I learnt and implemented digital design and Implementation flows including Synthesis, Clock Domain Crossing, Static Timing Analysis, Logical Equivalence Check.

Trainee Engineer for a 6 month company sponsored training in Logic Design domain at Veda IIT [July 2017 - January 2018].
During my course work I learn majorly about concepts - Advanced Digital Design, HDL Coding in Verilog and System Verilog, Logic Synthesis, Unix shell scripting, C, C++, Perl, TCL.

Software Engineer at Capgemini Information Technologies and Consultancy [August 2016 - July 2017]
In my tenure, I learn about the concepts in Object Oriented Programming in Java and implemented the same in the project.

Intern at Bhabha Atomic Research Center, Mumbai [June 2014 - July 2014]
During my internship, I learn about the approach and though in designing any digital system. Specifically, I worked on a Digital Pulse Width Modulation design.


Projects:
FIR Filter Design: Designed an FIR Filter using Rectangular , coded using Hardware Description Language (Verilog). Completed Synthesis, DFT, PD flows for the same. Find the details here: FIR Filter report
 

AMBA Advanced System Bus (ASB): Implemented RTL design for AMBA ASB for 3 Masters and 3 Slaves based on priority logic for Arbiter and Decoder. Please find the details here: AMBA ASB Research Paper

Design and Implementation of Pipelined processor for Image Compression through Burrows-Wheeler Transform: Implemented design for pipelined processor to achieve lossless image compression using Burrows-Wheeler Transform in Verilog and Matlab. Publication can be found here.  

Design and simulation of 16-bit 5 stage pipelined processor: A Processor with a set of 50 instructions was designed and implemented in Verilog to execute instructions in pipelined fashion with 5 stages (Fetch, Decode, Execute, Memory, Write-back).

Currently, my plan is to work on a design to take it from RTL stage to GDSII file. I have chosen an FIR filter as my project. I would start with RTL Design, verify it using a self-checking TB, synthesize the design into netlist. Further to get some understanding in scan insertion, I will insert scan chains and generate ATPG for the same, and further take it through the Physical Design stage to complete my understanding in Digital Design Flow. I will update the work soon.


To visit my Linkedin profile: https://in.linkedin.com/in/ankit-berde-a84b88106