Guidelines for synthesizable designs

You are allowed to write synthesizable as well as non-synthesizable design.

Synthesizable designs are the ones and the only category who can be mapped to a hardware.
Non-synthesizable designs, also known as models, cannot be mapped to a hardware. These designs are mostly used in creating test-benches, or can be used as a makeshift for library models during simulations.

There are 3 guidelines a designer should follow to develop a synthesizable module:

    1.  There should be a 1-to-1 mapping between signals or variables specified in the sensitivity list of a combinatorial always block and the signals used on RHS of that always block.
                                        Example:
                                           always@(sig1, sig2)
                                           begin
                                              sig_o = sig1 + sig2 ;
                                           end

    2.  In every 'if' or 'case' construct inside a combinatorial always block, you should cover all possible cases, or else latches would be inferred in the design.
                                        Example:
                                           if(sel)
                                              out1 = in1 ;
                                           else 
                                              out1 = in2 ;
                                           
       OR Make sure somewhere in the always block, the signal is getting assigned
                                        Example:
                                              out1 = in2 ;
                                           if(sel)
                                              out1 = in1 ;

    3.  Never assign a single variable in more that one always block.



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