Verilog Properties
Verilog language has evolved from C language and imbibing all the properties of C language, with an exception of 2 major differences.
2 Verilog Properties different from C language:
1. Non-sequential assignments:
If you want to write multiple 'assign' statements or 'always' blocks, it is not mandatory that sequence of statement will be followed. Every time the RHS of the assignment changes, the statement is executed, and as a consequences other statements can be executed if the LHS variable of this statement is used on RHS side of some assignment elsewhere.
2. Concurrency:
More than one statement/block can be executed at same simulation time parallely.
But, at processor level, it is still one statement at a time. But since output is displayed after all assignment statements are executed, we feel that all assignments are concurrent.
2 Verilog Properties different from C language:
1. Non-sequential assignments:
If you want to write multiple 'assign' statements or 'always' blocks, it is not mandatory that sequence of statement will be followed. Every time the RHS of the assignment changes, the statement is executed, and as a consequences other statements can be executed if the LHS variable of this statement is used on RHS side of some assignment elsewhere.
2. Concurrency:
More than one statement/block can be executed at same simulation time parallely.
But, at processor level, it is still one statement at a time. But since output is displayed after all assignment statements are executed, we feel that all assignments are concurrent.
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