Verilog datatypes and operators

Types of datatypes:
1. reg:
   A variable has to be declared of type 'reg' if it is assigned inside an always or initial block.
   A reg type variable will be synthesized into a flop.

2. wire:
   A variable has to be declared of type 'wire' if it is assigned in 'assign' statement, or if it is passed as actual argument in lower hierarchical instance.

 Operators:
Arithmetic:      +  -  *  /  **
Comparison:   >  >=  <  <=
Logical:            ~  &&  || 
Bitwise:            !  &  |  ^
Shift:                >> <<
Concat:            { }
Repetition:       n{}

 SIZE'VALUE:
For example: When we use a constant, we can determine the constant value in binary, octal, decimal, hexadecimal base.

 For example:
Binary: 4'b1010, 10'b1011_1100_01
Octal:   9'o247
Decimal: 6'd159
Hexadecimal: 16'h1F5B

 An underscore can be used as separator in between the value digits.

 SIZE determines the number of bits to be considered in the constant
' generally referred as 'tick'
b, o, d, h are representations for base (binary, octal, decimal, hexa respectively)
VALUE represents the value of constant in the base.

 If SIZE < bits required for VALUE: That many MSB's are truncated.
For example 2'b1011 is same as 2'b11.

 If SIZE > bits required for VALUE: MSB is copied for the remaining bits on the left.
For example 8'b1011 is same as 8'b1111_1011.

 Types of signals:
1. As a whole (default): Example- wire sig1
2. Part select: sig1[7:4]
3. Bit select: sig1[3] or sig1[i]



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