Case statement

The 'case' block is similar to 'if...else' block. It is more relevant when you have to choose among different combinations or patterns of same signal.

Three case blocks are supported by Verilog:

1. case
Syntax:

case(condition_signal)

condition1: block of statements ;

condition1: block of statements ;

.

.

.

default: block of statements ;

endcase

Here, block of statements -> if there are more than 1 statement, include in begin...end construct else simply mention the statement.
       default -> is optional but is specifically recommended when case statement is part of a combinatorial always block.
      Here, both 'x' and 'z' in condition statements are evaluated as literals.

Difference between 'case' and 'if':
If you would observe here, there is no priority among conditions, however, in 'if' construct, subsequent conditions are checked only if none of the prior conditions are not satisfied.
You would appreciate the difference even more when you think hardware. No priority as in the synthesis tool can optimize the logic in much faster and area optimized manner. There are many synthesis tool pragmas to indicate the same and leverage the power of synthesis.

2. casex
Syntax is similar to 'case' construct, only difference is that use of 'x' and 'z' are allowed in conditions, and 'x' and 'z' are evaluated as wildcards.

Example:
case(sig_in)
4'b00xx : sig_out = 2'd0 ;
4'b010x : sig_out = 2'd1 ;
4'b01xz : sig_out = 2'd3 ;
default : sig_out = 2'd3 ;
endcase

Here, if sig_in = 4'b0010, sig_out = 0
          if sig_in = 4'b0011, sig_out = 0
          if sig_in = 4'b0101, sig_out = 1
          if sig_in = 4'b0111, sig_out = 2
If there is an overlap in conditions, the one mentioned prior get priority.

2. casez
Syntax is similar to the above ones. The only difference is that, here, only 'z' in condition statement is evaluated as wildcard.
'x' in condition statement is still taken as literal.
So, in the immediate above example,
          if sig_in = 4'b0101, sig_out = 2, and only
          if sig_in = 4'b010x, sig_out = 1

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