RTL Design Introduction

History:
   -> Introduced for the first time in 1985.
   -> Commercialized and standardized in 1995.

 After this, ASIC designing started flourishing after advent of Verilog.

 RTL Design is only for functionality. Since, Verilog doesn't consider any delays, use of HDLs can and should be used only to verify specified functionality.

 Before Verilog, circuit design and testing was done on boards and on successful verification the design was fabricated in a fabrication unit. Thus, TEDIOUS.

 Therefore, RTL Designing was introduced as a software simulation solution before the Hardware.

 Thus,
determine an architecture of your design ->    determine the design ->    code functional behavior using RTL Design ->    Synthesize your design. This is front-end design flow for Digital ASIC and IP Designs.
Currently, the most widely used HDLs are:
1. Verilog
2. System Verilog

 Continue reading to know all about RTL Design using Verilog and System Verilog.



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