Types of Data paths

Types of data paths:

In any design, there can be only 4 types of data paths:
1.   Reg-to-Reg paths
2.   Input-to-Reg paths
3.   Reg-to-output paths
4.   Input-to-Output paths


Reg-to-Reg paths:

   Start point: CLK pin of a flop
   End point: D pin of a flop

Fig: Reg-to-Reg paths


DAT: tclk-q-A + tcomb
DRTSU: Tclk - tsu-B

where, Tclk = Clock period,

            tclk-q-A = Propagation Delay for Flop A from CLK pin to Q pin,

            tcomb = Combinational Path Delay,

            tsu-B = Setup time for Flop B.


For no Setup violation, DAT ≤ DRTSU


DRTHO: THO-B

where , THO-B = Hold time for Flop B

For no Hold violation, DAT ≥ DRTHO


The above analysis is true when no clock uncertainty or clock jitter is considered.
When clock uncertainty is considered, the above analysis can be framed as:

DAT: tclk-q-A + tcomb

DRTSU: Tclk - tsu-B + tuncertainty

DRTHO: THO-B + tuncertainty

where, Tuncertainty = Clock delay at destination flop’s clock pin with respect to source flop’s clock pin.        (Can be positive or negative).
While doing timing analysis, we can specify an uncertainty value. Timing tools consider a negative uncertainty for setup analysis and a positive value for hold analysis.
For example,
set_clock_uncertainty 250 CLK1 -setup
set_clock_uncertainty 200 CLK1 -hold
During analysis, tool uses -250 in DRTSU and +200 in DRTHO equations. Considering the worst case for each.


Now, adding clock jitter to above analysis:

DAT: tclk-q-A + tcomb

DRTSU: Tclk - tsu-B + tskew - tjitter

DRTHO: THO-B + tskew + tjitter

where, tjitter = Worst case Clock jitter at destination flop wrt to source flop’s clock pin.
These are the final equations, with the Setup and Hold inequalities are same as above.


Input-to-Reg paths:

Start point: Input port
End point: D pin of a flop


Fig: Input-to-Reg paths

DAT: Tin + tcomb
DRTSU: Tclk - tsu-B
where, Tclk = Clock period,
            Tin= Input delay outside to DUT,
            tcomb = Combinational Path Delay,
            tsu-B = Setup time for Flop A.
For no Setup violation, DAT ≤ DRTSU
DRTHO: THO-B
where , THO-B = Hold time for Flop A
For no Hold violation, DAT ≥ DRTHO


Reg-to-Out paths:
   Start point: CK pin of a flop

   End point: Output port
Fig: Reg-to-Output

DAT: tclk-q-A + tcomb + Tout
DRTSU: Tclk
where, Tclk = Clock period of clock wrt output delay,
            Tout= Output delay outside to DUT,
            tclk-q-A = Propagation Delay for Flop A from CLK pin to Q pin,
            tcomb = Combinational Path Delay,
For no Setup violation, DAT ≤ DRTSU
DRTHO: 0
For no Hold violation, DAT ≥ DRTHO

In-to-Out paths:

   Start point: Input port
   End point: Output port
Fig: Input-to-Output

DAT: Tin + Tcomb + Tout
DRTSU: Tclk
where, Tclk = Clock period of clock wrt output delay,
            Tin= Input delay outside to DUT,
            Tout= Output delay outside to DUT,
            tcomb = Combinational Path Delay,
For no Setup violation, DAT ≤ DRTSU
DRTHO: 0
For no Hold violation, DAT ≥ DRTHO

PS: As a self-study, you can modify above DAT and DRT equations by considering clock jitter and uncertainty.

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