Logical Synthesis Basic Timing Concepts
Basics:
Before, getting into synthesis of an RTL design, it is important to understand a few fundamental concepts of digital design.What is a flip-flop?
A flip-flop(or simply flop) is a design circuit that can store a bit of data. It stores the old data until a new data to be written into the flop is held stable at the input of the flop at the active edge of a clock signal to the flop. Depending upon the sensitivity of edge of the clock, a flop can be positive edge triggered or negative edge triggered.A more common implementation of flop circuit is formed by cascading of two similar(master-slave) latches operating at inverted clocks with respect to each other.
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| Fig: Flop |
Thus, in one clock level Master = Transparent & Slave = Opaque, in inverted clock level Slave = Transparent Master = Opaque.
Every flop has two timing windows: Setup and Hold.
What is Setup window?
A signal at data pin must be stable for a minimum time period(called setup window), just before the active edge of a clock signal.
To understand the existence of Setup period of a flop, we need to delve inside a flop.
Consider a positive level triggered Master latch which gets an inverted clock signal(at Enable pin) with respect to the clock pin of the flop for a positive edge triggered flop. Now, data signal utilizes some time to propagate from D pin to Q pin of master latch, and if the clock signal goes low within this propagation period, it may result in metastability, and is termed as setup violation. Thus, Setup time window is only limited to data propagation in Master latch.
Let us take an example to clear the Setup time concept:
At time t1, when the Enable or Clock pin of Latch is active, node D = 0, A = 1, B = 1, C = 0. Thus, Q = 0.
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| Fig: Master latch @ t1 |
At time t3 > t1, if the Clock pin of Latch is still considered active, if node D = 0 -> 1, then node A = 1 -> 0, B = 1 -> 0, C = 0 -> 1, Q = 0 -> 1.
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| Fig: Masterlatch @ t3 |
Now, if at time t2, where t1 < t2 < t3, if Clock or Enable pin of Master latch receives a toggle from 1 -> 0 (i.e. posedge at clock pin of flop), nodes B, Q, Qbar enter metastability state, and the output of the Master latch becomes indeterminate. Thus, the input and output of Slave latch, and in turn output of flop enters metastability.
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Thus, in this case, Setup window = Propagation delays of 1 inverted and 3 Nand gates.
The input at the D pin of flop should change before the start of Setup window to avoid any Setup violations.
Lets say, worst case scenario, for D(fall) => A(rise) + C(fall) + Qbar(rise) + Q(fall) : this is the worst time required for D-Q. Clk(fall) => B and C (rise) : this is worst time for Clk-Q
Now, suppose if D-Q(delay) = 5 and Clk-Q(delay) = 1,and if Clk(ff) @ 5 then Clk-Q @ 6 then D can only change prior to @ 1 => setup window = 4
if we increase Clk-Q(delay) of master latch by 4, Clk(ff) @ 5 then Clk-Q @ 10 then D can only change prior to @5 => Setup window = 0
if we increase Clk-Q(delay) of master latch further by 5, Clk(ff) @ 5 then Clk-Q @ 15 then D can only change prior to @ 10=> Setup window = -5
What is Hold window?
Unlike Setup time window, Hold time window is due to the time difference in the clock signals received at the Enable or Clock pins of Master and Slave latches. Thus, by controlling this time difference, Hold window could be controlled.
Now, consider the following example for better understanding of Hold window.
Suppose, the Slave’s Clock pin receives a non-inverted clock signal at time = t1, while the Master’s Clock pin receives an inverted clock signal at time = t2, where t2 > t1. For a time interval between t1 and t2, both Master and Slave latches are transparent. Thus, any data change at the D pin of flop in this interval might or might not reflect at the Q pin of Slave latch before the Master latch turns off. And, this interval is the Hold window.
The basic idea here is that when both the Master and the Slave latches of capture flop are transparent, the new data could disturb settling of old data (which is the actual data to be captured at the edge).
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| Fig: Timing diagram |
Now, if t1 > t2, the Hold window becomes negative. Also, if t1 = t2 the Hold window ceases existing.
Thus, data should change only after end of the Hold window to avoid any Hold violations.
What is clock latency?
Source latency: The relative propagation delay from PLL(which generates clock) output pin to point at which clock enters the design.
Network latency: The propagation delay from source of clock to last common point in clock path for source and destination flops.
-early and -late options: For Setup analysis, we consider the late value for source clock and early value for destination clock. Similarly, For Hold analysis, we consider the early value for source clock and late value for destination clock.
What is clock skew?
In a real design, clock signal will take some time to reach from its source (PLL, Flop) to any flop’s clock pin. Thus, in a data path, source flop and destination flop won’t receive the same clock at same instance. There would be some delay in clock triggered at destination flop’s clock pin to source flop’s clock pin. This delay is coined as ‘clock skew’ or ‘clock uncertainty’.Clock skew benefits Setup analysis, while it is a drawback for Hold analysis.
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| Fig: Clock Skew |
What is clock jitter?
During simulations, the clock will trigger at expected time intervals, even after considering clock skew. However, in the real world, clocks will not trigger at the clock pin of flops at expected times. There could be several reasons for this effect. One of them that I know is that, consider a clock signal in a net switching from low level to high level at a time instance. Now, suppose if there is another net adjacent to the clock net, which is at level 0. Due to the parasitic capacitance created at switching, the clock signal might take extra time to switch to level 1. Other way round, if the adjacent signal was a level 1, it would have supported the switching, and switching time could have reduced due to this. Thus, clock signal edges might not be accurate to ideal simulation results. This delay can be termed as ’clock jitter’.Clock jitter can be positive or negative and cannot be determined exactly.
So, only worst case values are considered for analysis.
A negative value is considered for Setup analysis. Since the worst case for Setup would be when source clock is delayed and destination clock is advanced. While, a positive value is considered for Hold analysis. Since the worst case for Hold would be when source clock is advanced and destination clock is delayed.
Recovery Time:
Once you have understood the Setup time window and its causes, understanding Recovery time is a piece of cake. The Recovery time window concept borrows the concept from Setup time. Only data change is to be replaced with deassertion of asynchronous reset. By asynchronous reset, I mean that assertion of reset is asynchronous, while deassertion is still synchronous to the clock.Recovery time = time after deassertion of reset for which the signal at reset pin should be stable before the active edge of the clock.
Basically, if the reset is deasserted in Recovery window of the clock, you cannot be sure whether reset deassertion was acknowledged by the clock or not. Now, the concept of how it can cause metastability is same as in Setup time theory.
Removal Time:
This concept is borrowed from Hold time window.Removal Time = time before deassertion of reset for which the signal at reset pin should be stable after the active edge of the clock.
The flop is in reset state, and an active edge of clock triggers, now if the reset is deasserted in the Removal window, you cannot be sure whether reset deassertion was acknowledged by the clock or not.
What is a Multi-cycle path?
Data-paths starting at the launch edge of the launch clock will reach the destination flop after ‘N’ active edges of the capture clock, for a multi-cycle = N.
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| Figure: Timing Diagram for Multicycle of 3 |
Figure above shows a multi-cycle of 3. By default, when multi-cycle for setup is specified, the edge before the capture edge on the capture clock becomes your hold analysis edge.
To obtain above exception for analysis, use following command:
set_multicycle_path 3 -setup -from [lauch_flop] -to [capture_flop]
-setup option: Indicates that Setup analysis is done using mentioned path_multiplier (integer)
The capture edge is moved to the mentioned edge from the launch edge. So, if path_multiplier = 3, the capture edge is moved by 3 edges from the launch edge i.e. 2 edges forward of default single cycle capture edge.
Note: changing path_multiplier for Setup sets default hold capture edge as well. You need to override the hold capture edge after the setup command to change its default position.
-hold option: Indicates that Hold analysis is done using mentioned path_multiplier (integer).
The default hold edge is moved by path_multiplier number of edges..
-start: indicates that the mentioned path_multiplier value is with respect to launch clock.
when used with -setup, the launch edge considered for setup analysis is moved backward to the mentioned path_multiplier cycles.
when used with -hold, the launch edge considered for hold analysis is moved forward by mentioned path_multiplier cycles.
-end: indicates that the mentioned path_multiplier value is with respect to capture clock.
when used with -setup, the capture edge considered for setup analysis is moved forward to the mentioned path_multiplier cycles.
when used with -hold, the capture edge considered for hold analysis is moved backward by mentioned path_multiplier cycles.
False paths:
A logical path can exist between the two points, though will not be analyzed for timing if defined false_path. The disable_timing command removes the specified point from timing analysis, though false_path adds an exception, i.e. delays are calculated for the path only slack error is not reported.
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