Overview of Steps in Synthesis flow


Fig: Synthesis steps



1. Environment Setup:Setting up variables and attributes. Some attributes like hdl_search_path or lib_search_path are to be set before reading design and libs.

2. Read libraries:Specify all the standard cell libraries and analog module’s timing parameters.

3. Read design files:Specify all the design files to be read.

4. ElaborateTool expands the design hierarchy here.

5. Read SDC:Read the clock, I/O Delay constraints, etc.

6. Specify Design Constraints:All Design Constraints which the tool cannot violate while synthesis go here.

7. Specify Optimization ConstraintsThe tool should behave in a directed manner according to the designer’s expectations. The designer should express the intent here. Remember, not to over-constrain or under-constrain the design.

8. SynthesizeThe tool attempts synthesis or incremental synthesis in this step.

9. Report Timing to check if timing, power, area requirements are metIf no, go to step 10 and re-synthesize the top module. If yes, go to Step 11.

10. Modify constraints or design:If the timing, area, or power requirements are not met, modify the constraints, or redesign the critical paths or modules to meet the constraints.

11. Write Out Netlist and SDC:This is the final step. Simply write out all the reports, sdc and netlist to provide it to Physical Design team. This is the end of Logical Synthesis.

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