Detailed Steps in Synthesis

1. Environment Setup:

Setting up of directory path variables, multi-threading attributes, tool licence variables, etc fall under this category. This is required to make the script generic so that the run can adapt to any design with minimum efforts.

2. Reading libraries:

A library typically has actual cells and its timing, power and area related information. These cells will be actually fabricated on the IC, and is thus provided by the Fabrication Vendor.
Libraries can be classified as:

Target libraries: Used in synthesis operation by the tool in implementing RTL to gates
Link libraries: Tool uses this libraries when resolving references in your design.
Symbol libraries: It has symbols for the cells to be viewed in schematic
Designware / Synthetic libraries: All the operators in your design will be mapped to cells from these libraries.

A library has auxiliary information about wireload models, wireload modes, operating conditions. I will explain later in the blog about how these parameters affect timing and power.
A library by default is targeted for a specific operating condition (PVT - Process Voltage Temperature), however we can overwrite the default operating condition with a command. For eg:

set_db [get_db / .operating_conditions ] .voltage V3

In a typical library, there exist 3 types of standard cells: High Threshold Voltage (HVT), Standard Threshold Voltage (SVT), Low Threshold Voltage (LVT).

Timing optimized: LVT > SVT > HVT

Power optimized: HVT > SVT > LVT

Why so?

SVT cells have a lower sub-threshold voltage level as compared to HVT cells. While LVT cells have the lowest sub-threshold voltage level among all.

Now, it is known that only one set of transistor is ON at a given time, i.e. either NMOS or PMOS. However, even when the transistor is in OFF state, a small amount of current flows through the transistor, known as sub-threshold or leakage current. This current is maximum when transistor is just below the sub-threshold level in OFF state.

Now in LVT cells, this sub-threshold voltage level is reduced as compared to SVT cells, and SVT cells have a lower sub-threshold voltage level with respect to HVT cells. Thus, the leakage current is more in LVT cells, than in SVT cells, than in HVT cells.

Though one advantage of LVT cells is that since the sub-threshold voltage is lower comparatively, the transistor will require less time to switch between states, and thus is time optimized while switching over SVT or HVT cells.

Voltage Scaling: If we are using multiple voltage sources in a design, we can divide regions in our design based on library domains, the tool will optimize each domain to operate in the mentioned voltage level.

Following are the steps for dividing design in domains:

Create domains -> Read libs for each domain -> Read design, elaborate and apply constraints -> Map domains to the design -> Synthesize.

Keep reading for detailed analysis on this method of optimization.

3. Reading design files:

The design related files are to be read by the tool using the following command
read_hdl {file_list} -define {DEFINE1 …}

Generally, the file list will be large and thus is stored in a file, and that file is supplied as an argument to the read_hdl command using -f option. The files list can be embedded inside other files too.
The tool, in this step, clubs all the design files and checks for any syntax errors in the code. The design should be compile free to proceed.

4. Elaborate:

In this step the tool expands the design hierarchy and creates a structural design, forms all the inter-module connections, checks for semantic errors.
By the end of this step, the design is still in unmapped RTL format.
Before this step, the engineer should specify any grouping or ungrouping intents for certain modules which are in the same hierarchy. The tool may add or dissolve levels of hierarchy based on the commands. For instance, if a group of blocks’ ‘group’ attribute is same, the tool considers these modules for grouping and creates a wrapper around these blocks before placing it in it’s parent module.

5. Read SDC

An SDC is file with design constraints which can include but not restricted to:

Adding clock definitions on top level ports as well pins of sub-modules.
Clock related constraints including uncertainty, skew, transition time delay.
Input/Output delays, transition time delays, loads on ports.
Assigning constant values to certain pins or ports.
Specifying Multi-cycle or false path constraints on certain paths.

It is recommended that for best results, not to over or under constrain the design.
Based on these design constraints, tool approaches with its synthesis techniques, memory and processing utilizations.

6. Specify Design Constraints:

Design constraints are basically to specify the maximum or minimum capabilities the design can handle.
These set of constraints include following commands:

set_max_transition
set_max_load
set_max_fanout

The tool cannot violate the constraints, and tries to synthesize the design accordingly without any Design Rule Checks (DRC) violations. To prevent any net, pin or port from DRC, make it an ideal network.

7. Specify Optimization Constraints:

Based on these constraints the tool can be directed to optimize the design.
It is based on the designer’s intent the tool optimization techniques and directions can be controlled.
For example: The tool can better optimize a time critical design if it can dissolve the hierarchy and optimize the data path for timing across the boundary of sub-modules. The designer can intent the tool to do so using optimization constraints. However, doing so may affect Logical Equivalence Check flows. And thus, depending upon the intent optimization constraints can be applied.
Optimization Constraints can include following commands but not restricted to:

preserve {lib_cell_instance/ instance/ module}
group {inst1 inst2 ...}
ungroup {inst1}
set_db [get_db modules *] .boundary_optimization TRUE
set _db / .opt_effort HIGH ##similarly for generic and map effort
set _db / .leakage_power_effort HIGH ##similarly for dynamic power

Optimization constraints can be subdivided at four levels of optimization:

RTL Optimization: It can include enabling resource sharing
Global Mapping: It includes using or preventing Technology dependent cells.
Global Optimization: It includes usage of high speed cells on time critical paths, or low power cells on time sparing data paths.
Incremental Optimization: Can include usage of multi-bit cells.

8. Synthesis:

syn_generic:

The elaborated design will be mapped to generic gates and a netlist can be written out post this step.
If syn_generic command issue on an RTL, it implements RTL optimization and synthesizes it to generic gates.If syn_generic command issue on a mapped netlist, it unmaps the technology dependent netlist. The command has no impact when issued on generic netlist.

What kind of RTL Optimization?

The tool can locate critical paths in the RTL, or an inept implementation of a logic in RTL and use it’s optimization techniques to further optimize the synthesis.
RTL Optimization can include but not restricted to following optimization techniques:
Sharing Optimization:

Fig: Sharing Optimization

The MUX implementation takes less area than an adder’s implementation, in that case, the tool can share the adder by positioning the MUX behind adder.

Critical Path Optimization:

Fig: Critical path Optimization

The critical paths in the original RTL Implementation is positioned such that as little data path comes under critical data path.

syn_map:

The netlist with generic gates are mapped to technology dependent cells. Cells from multiple technology libraries can be picked up by the tool depending upon the attributes specified by the designer.
syn_map is done on a generic netlist, where the command maps the design to technology dependent cells.
There are many implementation cells of the same logic function. For instance, an OR gate cell can be x1, x2, x4, x8… drive strength. Same OR gate cells can be available in HVT, SVT, or LVT libraries.

syn_opt:

Tool uses optimization techniques and algorithms it has to optimize the design for time, power and area, with time optimization given highest priority over other 2 factors.
For example, in this step, tool can implement multibit cells wherever it can. A library can have multibit cells, which can be shared my multiple signals for flopping data provided they can share the auxiliary pins in a flop (like SET, RESET). Multibit cells are more power and area optimized compared to its counterpart.
Or the tool can implement clock gating techniques provided clock_gating attribute is set to TRUE, abiding to min and max limits of flops. For instance, if the tool finds a group of flops receiving same ‘Enable’ signal, the tool can eliminate this signal in the flop pin, and connect it to a clock gating cells which it will auto instantiate. Such, clock gating techniques can help save a significant amount of power dissipated.

syn_opt -incremental:

Designer can optimize the design further by using incremental switch of syn_opt.
The tool partitions the design based on critical designs, and thus can concentrate it’s analysis in critical portions of the design, with reduced run-time and memory. For example, critical paths are time optimized with higher speed grade combinational logic, given that user_speed_grade attribute is set to FAST or VERY_FAST.

9. Reports:

Important report to be generated and looked for:

report_timing
report_area
report_power
report_qor

Check for any timing violations, because with negative slack present in the design, there is no point in going to the next step.
If the timing is not met, the designer can do the following:

Change optimization settings so as to go for a more rigorous optimization run. Sometimes implementing the synthesis run again and again incrementally may lessen the slack.
Apply less rigorous design constraints, giving the tool more freedom to synthesize the design.
Go for a RTL change. See if one can implement the logic with a more skilled approach.
Consider making the SDC less severe. Try by reducing design clock frequency, or input/output delays. These changes mean change in specification, thus should be considered as a last option if all the above provisions don’t work.

Remember, only Setup slack is to be met in Logical Synthesis. Hold violations can be solved by Physical Layout Engineers.

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Ankit Berde