Issues in Clock Domain Crossings

1. Meta-stability:
   If input of the destination flop changes close to active edge it can cause metastability. Output of destination flop may be dangling to a metastable state, or it can be oscillating for a while, and settle to a stable value which is indeterminate.

   Consequences:
1. If output of the destination flop is oscillating in metastable state, it can cause heating, power loss.
2. Different fanouts of the source flop may capture different values.
3. Destination flop output may settle to a new value or to old value which is unpredictable.

   Solution: Multi-flop synchronizers - only condition is that input data must be stable for a minimum time = tclk + tsu + tho + tskew

2. Data-loss

   Data in source clock domain should be kept constant for at least 1 CP of destination flop. In other words, when there is a transition in input of destination flop it should stay constant so that minimum one destination clock domain edge captures data without any setup or hold violations.

Solution: Use a FSM - to control data change.

               Or Handshake synchronizers or Asynchronous FIFOs (I have explained these in later posts).

3. Data-incoherency:

   For a multi bit signal, it can be possible that some of the bits get captured on immediate capture edge and some on the next capture edge.

   Solution: Use Enable signal as a qualifying signal which is to be synchronized first in the destination domain and this synchronized one can be used as a qualifying signal for the data signal.

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