Types of Synchronizers

Multi-flop synchronizer:

The signal from source clock domain should be connected directly to a synchronizer in destination clock domain flop without any combinational logic in between.

This signal in destination domain is not metastability issues free. Therefore, this signal cannot be directly used in destination domain.

It is passed through at least one more flop in destination domain referred to as depth of synchronizer. Thus, a synchronizer must have at least a depth = 2 (i.e. 2 flops in destination clock domain).

The final output of a synchronizer is free of metastability issues since it’s prior flop is synchronous to it.

Fig: Multi-flop synchronizer

In this figure, CLK1 and CLK2 are in different domains.

Condition is to not to include in combinational logic while domain transition or inside synchronizer. Since the combinational logic can have multiple propagation times and can cause data loss issues. So, first transfer the signal in destination domain and then use any logic to manipulate the data.

Did you notice that the problem of data loss is still prevailing. The only way around it is to follow the above timing conditions for prevention.

Multi-bit synchronizer:

A qualifying signal, let's say Enable, is synchronized in destination clock domain. And it is used to accept new data from source clock domain.

Fig: Multi-bit synchronizer

Condition is:

1. Till Enable signal is synchronized in destination domain, data signal has to be kept stable.
2. Circuit/Logic should be resistant to data loss, especially in transition from fast to slow clock.

The logic solves problem of data-incoherency. Either all the bits of a signal are transitioned or none. Thus eliminating any possibility of wrong data being circulated even for a while.

PS: You can use a simple synchronizer for multiple bits when the signal is gray coded and signal transition happens incrementally only.

Asynchronous FIFO:

The basic idea in asynchronous FIFO is that write domain starts with writing data into an empty FIFO, and after some cycles read domain can start reading data to prevent FIFO overflow, till it empties reading all data to prevent FIFO underflow.

Fig: Asynchronous FIFO

If WR signal is given by logic in write domain, the FSM in write domain, is used to prevent overflow in FIFO. Write counter starts incrementing.
It is only when:

(wr_ptr + 1 == rd_ptr_sync) && (wr) = FIFO_FULL

Write FSM issues Enable signal for wr_ptr counter, which is directly connected to wr_addr of FIFO memory. Write FSM also issues a wr_en to memory upon which data can be written into memory.

Read domain can start reading any cycle after at least one successful write is completed by the write domain.

If RD signal is given by logic in read domain, the FSM in read domain, is used to prevent underflow in FIFO. Read counter starts incrementing.

It is only when: 

(rd_ptr + 1 == wr_ptr_sync) && (rd) = FIFO_EMPTY

Read FSM issues Enable signal for rd_ptr counter, which is directly connected to rd_addr of FIFO memory. Read FSM also issues a rd_en to memory upon which data can be written into memory.

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