Basic concepts in CDC

What is metastability?
The state where the output of a memory can be anywhere between VOH and VOL because the input of the flop is itself between VIH and VIL at the trigger of active edge of the clock.
   It can occur due to many reasons like: setup or hold violation, race around condition.

Example: Take an example of a ball placed at the very top of a hill. Now the ball can be considered to be in a metastable state, since the exact movement or state of the ball cannot be predicted accurately. The ball could tilt and fall onto any side. Taking this analogy, when in metastable state, the output of the flop becomes indeterminate.
//Image comes here Metastability_example.
Fig: Metastability example


Take another specific example: Metastability in action:

Consider, a time = t1, where the Master latch of a flop is in Transparent state, which means, Enable pin or clock signal at Master latch is HIGH. Therefore, transition at D-input from 0->1 is accepted.
Fig: Master latch transitioning at time = t1


At time = t2, as a result, transitions 1->0 and 0->1 are seen at points B and C respectively.


Fig: Master latch transitioning at time = t2

At time = t3, transitions 1->0 and 0->1 reach points Qbar and Q. However, let's say at this point, when the transitions at mentioned points have still not taken complete effect, we see a 1->0 transition at CLK pin of Master latch. Now, the Master latch is switching to HOLD state.


Fig: Master latch transitioning at time = t3
At time = t4, since the transition at Qbar point is in nascent state, it can still be assumed to be a logic 1. Point B again oscillates to logic 1.


Fig: Master latch transitioning at time = t4

At time = t5, Point Q oscillates back to logic 0, and as a consequence tries to pull back Qbar to logic 1 which was transitioning to logic 0. Now, at time = t5, if Qbar had already reached a strong logic 0. It will oscillate back Q to logic 1, and the oscillation chain goes on till the circuit settles down to an indeterminate stable state.

Fig: Master latch transitioning at time = t5



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