Types of data paths with respect to CDC

Types of paths:

There can be 2 types of data-paths in a design:

1. Synchronous paths
2. Asynchronous paths

Synchronous paths:

   The paths existing between same clock domain are termed as synchronous paths, i.e. the source and destination points are clocked by a clock derived from a single PLL or any other clock source.

Synchronous paths can be further classified as:

1. Where fsource = fdest: Efforts should only be taken to keep such paths STA clean.
2. Where either clock can be an integral or rational multiple of the other
Such paths should be STA clean, and additionally, such paths can face a problem of data loss in paths involving data transition from fast to slow clocks.
           Care should be taken to implement an FSM as to not overwrite the incoming data at                    source flop till it is read at destination flop.
           Setup analysis is done on a launch-capture edge closest to each other while, Hold                       analysis is done on a launch-capture edge farthest from each other, with capture                         following the launch edge in time.

Asynchronous paths:

   The paths involving a inter-clock domain data transition.
   The source clock and destination clock are derived from different PLLs.   There cannot be any Timing analysis done on such paths, given to the mere fact that there can be no defined relationship between the two clocks in the real world.
   A proven synchronizer is implemented at the domain crossing, verified using a CDC tool and during timing analysis the path is assumed to be timing violation free.

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